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6 bit 384 channel rsds tft-lcd source driver nov. 2002. ver. 0.3 S6C1104
S6C1104 6 bit 384 channel rsds source driver 2 introduction the S6C1104 is a source driver suitable for reduced swing differential signaling(rsds) digital interface. it converts 18-bit digital data into the analog voltage for 384 channels, charging each sub-pixel to the correct gray level corresponding to the digital value. the rsds path to the panel timing controller contributes toward lowering radiated emi, reducing system power consumption and eliminates one of the two pixel busses used in typical xga, sxga tft lcd panels. this single 9-bit differential bus conveys the 18-bit color data for xga, sxga panels. features ? tft active matrix lcd source driver lsi ? 64g/s is possible through 10 (5 by 2) external power supply and d/a converter ? both dot inversion display and n-line inversion display are possible ? compatible with gamma-correction ? charge sharing function ? logic supply voltage[vdd1] : 2.7 to 3.6 v ? lcd driver supply voltage[vdd2] : 7.0 to 12.0 v ? output dynamic range: vss2+0.2v to vdd2-0.2v ? maximum operating frequency: fmax=85 mhz (internal data transmission rate at 2.7 v operation) ? output: 384 outputs ? reduced swing differential signaling(rsds) interface for low power consumption and low emi. ? minimum rsds input swing level(clkp, clkn, datap, datan): 100mv ? data bus interface control pin (datpol) ? tcp or cof supported
6 bit 384 channel rsds source driver S6C1104 3 block diagram data register rsds receiver output buffer r-dac data latches 128 bit shift register pol vgma1 to vgma10 clk1 d00p d00n d01p d01n d22p d22n clkp clkn shl 6 6 6 6 6 6 dio1 dio2 6 6 6 6 6 6 y1 y2 y3 y382 y383 y384 datpol 10 figure 1. S6C1104 block diagram
S6C1104 6 bit 384 channel rsds source driver 4 pin assignments testi1 testo1 dio1 d00n d00p d01n d01p d02n d02p y1 y2 y3 y4 y5 y6 y7 y8 y10 y11 y12 y372 y373 y374 y375 y376 y377 y378 y379 y380 y381 y382 y383 y384 y9 pol clk1 clkn clkp vss1 vgma1 vgma2 vgma3 vgma4 vgma5 vss2 vdd2 vgma6 vgma7 vgma8 vgma9 vgma10 shl vdd1 d10n d10p d11n d11p d12n d12p d20n d20p d21n d21p d22n d22p dio2 testo2 testi2 datpol S6C1104 output 384 input 44 figure 2. S6C1104 pin assignments
6 bit 384 channel rsds source driver S6C1104 5 pin descriptions symbol pin name description vdd1 logic power supply 2.7 to 3.6 v vdd2 driver power supply 7.0 to 12.0 v vss1 logic ground ground (0 v) vss2 driver ground ground (0 v) y1 to y384 driver outputs the d/a converted 64 gray-scale analog voltage is output. d0p<0:2> d0n<0:2> d1p<0:2> d1n<0:2> d2p<0:2> d2n<0:2> rsds data input total data lines consist of 18 data bus. (6-bit digital, 3 colors(r, g, b) and 2 differential input pairs) the 3-bit differential input pairs generate the internal 6-bit data through the comparison between dxxp and dxxn. shl shift direction control input this pin controls the direction of shift register in cascade connection. when shl=h: dio1 input, y1 y384, dio2 output when shl=l: dio2 input, y384 y1, dio1 output dio1 start pulse input/output shl=h: used as the start pulse input pin. shl=l: used as the start pulse output pin. dio2 start pulse input/output shl=h: used as the start pulse output pin. shl=l: used as the start pulse input pin. datpol data inversion input datpol= l: no inversion datpol= h: data polarity inversion ( datpol must be fixed vss1 or vdd1.) pol polarity input pol=h: the reference voltage for odd number outputs are vgma1 to vgma5 and those for even number outputs are vgma6 to vgma10. pol=l: the reference voltage for odd number outputs are vgma6 to vgma10 and those for even number outputs are vgma1 to vgma5. clkp clkn rsds shift clock input the rsds clock input pairs generate the internal shift clock, clk2, through the comparison between clkp and clkn. clk1 latch input S6C1104 clears 128 shift registers at the rising edge of clk1 and outputs the analog data to the each channel at the falling edge. vgma1 to vgma10 gamma corrected power supplies input the gamma corrected power supplies from external source. vdd2>vgma1>vgma2> >vgma9>vgma10>vss2 keep power supplies unchanged during the gray-scale voltage output. testi1/o1, testi2/o2 amp test input/output these pins are used for amp test. testi1(=testi2)=l : normal operation mode
S6C1104 6 bit 384 channel rsds source driver 6 operation description rsds receiver and demux the S6C1104 adapts the rsds interface for emi solution. the internal rsds receiver block operates the comparison between the transmitted differential input pair data. the input data lines from the timing controller to the rsds receiver consist of 6-bit digital, 3 colors, 1 port, 2 differential pairs(dxxp/dxxn). the input common mode voltage range at the rsds receiver is 1.2v. the differential data and clock signals from the panel timing controller arrive at the S6C1104 as multiplexed, even and odd data fields. (i.e., the data is 2:1 multiplexed). the nominal peak to peak swing of this data is 200mv across a termination resistor. rsds data bus interface control datpol controls the internal data inversion. when datpol=?h?, the internal data is inverted. the inverted data is the same that the rsds receiver operates the comparison between the cross-transmitted differential input pair data. using the data inversion input pin, datpol, the rsds data bus interface can be changed. display data transfer when dio1 (or dio2) pulse is loaded into the internal latch on the falling edge of clkp, dio1 (or dio2) pulse enables the operation of data transfer, so display data is valid on the 2nd falling edge of clkp. once all the data of 384 channels is loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though clkp is provided until next dio1 (or dio2) input. when next dio1 (or dio2) is provided, new display data is valid on the 2nd falling edge of clkp after the rising edge of dio1 (or dio2). extension of output output pin can be adjusted to an extended screen by cascade connection. when shl="l", connect dio1 pin of the previous stage to the dio2 pin of the next stage and all the input pins except dio1 and dio2 are connected together in each device. when shl="h", connect dio2 pin of the previous stage to the dio1 pin of the next stage and all the input pins except dio2 and dio1 are connected together in each device. relationship between input data value and output voltage the lcd drive output voltages are determined by the input data and 10 (5 by 2) gamma corrected power supplies (vgma1 to vgma10). besides, to be able to deal with dot line inversion when mounted on a single-side, gradation voltages with different polarity can be output to the odd number output pins and the even number output pins. among 5-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity with respect to the common voltage, for the respective 5 gamma corrected voltages of vgma1 to vgma5 and vgma6 to vgma10.
6 bit 384 channel rsds source driver S6C1104 7 vcom input data vgma1 vgma2 vgma3 vgma4 vgma5 vgma10 00h 08h 10h 18h 20h 28h 30h 38h 3fh vss2 vdd2 vgma9 vgma8 vgma6 vgma7 figure 3. gamma correction curve
S6C1104 6 bit 384 channel rsds source driver 8 table 1. resistor strings (r0 to r62, unit: ? ? ? ? ) name value name value name value name value r0 1800 r16 120 r32 100 r48 120 r1 1000 r17 110 r33 100 r49 120 r2 700 r18 110 r34 100 r50 130 r3 600 r19 110 r35 100 r51 130 r4 500 r20 100 r36 100 r52 140 r5 400 r21 100 r37 100 r53 140 r6 400 r22 100 r38 100 r54 150 r7 300 r23 100 r39 100 r55 150 r8 300 r24 100 r40 100 r56 180 r9 200 r25 100 r41 100 r57 210 r10 200 r26 100 r42 100 r58 250 r11 150 r27 100 r43 110 r59 300 r12 150 r28 100 r44 110 r60 500 r13 130 r29 100 r45 110 r61 700 r14 130 r30 100 r46 110 r62 900 r15 120 r31 100 r47 120 total r : 14510 ? the S6C1104 has on-chip dividing resistors. the gamma correction voltage input pins are divided into two parts. each part is connected in series with resistors. each of these resistor series has a total typical value of 14510 ? . note that since these voltages are resistor divided internally, the voltages applied to the vgman pins should be applied through a low-impedance circuit. if the voltages are directly applied by the resistor divider, the desired output voltages may not result (recommend you to use operational amplifier). vgma1 r1_2 (7080 ? ) external gamma correction voltage generating circuit ic internal circuits vgma2 vgma3 vgma4 vgma5 vgma6 vgma7 vgma8 vgma9 vgma10 r2_3 (1650 ? ) r3_4 (1660 ? ) r4_5 (4120 ? ) r6_7 (4120 ? ) r7_8 (1660 ? ) r8_9 (1650 ? ) r9_0 (7080 ? ) data 3fh 00h 3fh 00h
6 bit 384 channel rsds source driver S6C1104 9 table 2. relationship between input data and output voltage value input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 00h 01h 02h 03h 04h 05h 06h 07h 0 0 0 1 1 1 vh0 vh1 vh2 vh3 vh4 vh5 vh6 vh7 vgma1 vgma1+(vgma2-vgma1) 1800/7080 vgma1+(vgma2-vgma1) 2800/7080 vgma1+(vgma2-vgma1) 3500/7080 vgma1+(vgma2-vgma1) 4100/7080 vgma1+(vgma2-vgma1) 4600/7080 vgma1+(vgma2-vgma1) 5000/7080 vgma1+(vgma2-vgma1) 5400/7080 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 0 0 1 1 1 1 vh8 vh9 vh10 vh11 vh12 vh13 vh14 vh15 vgma1+(vgma2-vgma1) 5700/7080 vgma1+(vgma2-vgma1) 6000/7080 vgma1+(vgma2-vgma1) 6200/7080 vgma1+(vgma2-vgma1) 6400/7080 vgma1+(vgma2-vgma1) 6550/7080 vgma1+(vgma2-vgma1) 6700/7080 vgma1+(vgma2-vgma1) 6830/7080 vgma1+(vgma2-vgma1) 6960/7080 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 10h 11h 12h 13h 14h 15h 16h 17h 0 1 0 1 1 1 vh16 vh17 vh18 vh19 vh20 vh21 vh22 vh23 vgma2 vgma2+(vgma3-vgma2) 120/1650 vgma2+(vgma3-vgma2) 230/1650 vgma2+(vgma3-vgma2) 340/1650 vgma2+(vgma3-vgma2) 450/1650 vgma2+(vgma3-vgma2) 550/1650 vgma2+(vgma3-vgma2) 650/1650 vgma2+(vgma3-vgma2) 750/1650 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 0 1 1 1 1 1 vh24 vh25 vh26 vh27 vh28 vh29 vh30 vh31 vgma2+(vgma3-vgma2) 850/1650 vgma2+(vgma3-vgma2) 950/1650 vgma2+(vgma3-vgma2) 1050/1650 vgma2+(vgma3-vgma2) 1150/1650 vgma2+(vgma3-vgma2) 1250/1650 vgma2+(vgma3-vgma2) 1350/1650 vgma2+(vgma3-vgma2) 1450/1650 vgma2+(vgma3-vgma2) 1550/1650 note: vdd2>vgma1>vgma2>vgma3>vgma4>vgma5
S6C1104 6 bit 384 channel rsds source driver 10 table 2. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 20h 21h 22h 23h 24h 25h 26h 27h 1 0 0 1 1 1 vh32 vh33 vh34 vh35 vh36 vh37 vh38 vh39 vgma3 vgma3+(vgma4-vgma3) 100/1660 vgma3+(vgma4-vgma3) 200/1660 vgma3+(vgma4-vgma3) 300/1660 vgma3+(vgma4-vgma3) 400/1660 vgma3+(vgma4-vgma3) 500/1660 vgma3+(vgma4-vgma3) 600/1660 vgma3+(vgma4-vgma3) 700/1660 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 1 0 1 1 1 1 vh40 vh41 vh42 vh43 vh44 vh45 vh46 vh47 vgma3+(vgma4-vgma3) 800/1660 vgma3+(vgma4-vgma3) 900/1660 vgma3+(vgma4-vgma3) 1000/1660 vgma3+(vgma4-vgma3) 1100/1660 vgma3+(vgma4-vgma3) 1210/1660 vgma3+(vgma4-vgma3) 1320/1660 vgma3+(vgma4-vgma3) 1430/1660 vgma3+(vgma4-vgma3) 1540/1660 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 30h 31h 32h 33h 34h 35h 36h 37h 1 1 0 1 1 1 vh48 vh49 vh50 vh51 vh52 vh53 vh54 vh55 vgma4 vgma4+(vgma5-vgma4) 120/4120 vgma4+(vgma5-vgma4) 240/4120 vgma4+(vgma5-vgma4) 370/4120 vgma4+(vgma5-vgma4) 500/4120 vgma4+(vgma5-vgma4) 640/4120 vgma4+(vgma5-vgma4) 780/4120 vgma4+(vgma5-vgma4) 930/4120 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh 1 1 1 1 1 1 vh56 vh57 vh58 vh59 vh60 vh61 vh62 vh63 vgma4+(vgma5-vgma4) 1080/4120 vgma4+(vgma5-vgma4) 1260/4120 vgma4+(vgma5-vgma4) 1470/4120 vgma4+(vgma5-vgma4) 1720/4120 vgma4+(vgma5-vgma4) 2020/4120 vgma4+(vgma5-vgma4) 2520/4120 vgma4+(vgma5-vgma4) 3220/4120 vgma5
6 bit 384 channel rsds source driver S6C1104 11 table 2. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 00h 01h 02h 03h 04h 05h 06h 07h 0 0 0 1 1 1 vl0 vl1 vl2 vl3 vl4 vl5 vl6 vl7 vgma10 vgma10+(vgma9-vgma10) 1800/7080 vgma10+(vgma9-vgma10) 2800/7080 vgma10+(vgma9-vgma10) 3500/7080 vgma10+(vgma9-vgma10) 4100/7080 vgma10+(vgma9-vgma10) 4600/7080 vgma10+(vgma9-vgma10) 5000/7080 vgma10+(vgma9-vgma10) 5400/7080 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 0 0 1 1 1 1 vl8 vl9 vl10 vl11 vl12 vl13 vl14 vl15 vgma10+(vgma9-vgma10) 5700/7080 vgma10+(vgma9-vgma10) 6000/7080 vgma10+(vgma9-vgma10) 6200/7080 vgma10+(vgma9-vgma10) 6400/7080 vgma10+(vgma9-vgma10) 6550/7080 vgma10+(vgma9-vgma10) 6700/7080 vgma10+(vgma9-vgma10) 6830/7080 vgma10+(vgma9-vgma10) 6960/7080 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 10h 11h 12h 13h 14h 15h 16h 17h 0 1 0 1 1 1 vl16 vl17 vl18 vl19 vl20 vl21 vl22 vl23 vgma9 vgma9+(vgma8-vgma9) 120/1650 vgma9+(vgma8-vgma9) 230/1650 vgma9+(vgma8-vgma9) 340/1650 vgma9+(vgma8-vgma9) 450/1650 vgma9+(vgma8-vgma9) 550/1650 vgma9+(vgma8-vgma9) 650/1650 vgma9+(vgma8-vgma9) 750/1650 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 0 1 1 1 1 1 vl24 vl25 vl26 vl27 vl28 vl29 vl30 vl31 vgma9+(vgma8-vgma9) 850/1650 vgma9+(vgma8-vgma9) 950/1650 vgma9+(vgma8-vgma9) 1050/1650 vgma9+(vgma8-vgma9) 1150/1650 vgma9+(vgma8-vgma9) 1250/1650 vgma9+(vgma8-vgma9) 1350/1650 vgma9+(vgma8-vgma9) 1450/1650 vgma9+(vgma8-vgma9) 1550/1650 note: vgma6>vgma7>vgma8>vgma9>vgma10>vss2
S6C1104 6 bit 384 channel rsds source driver 12 table 2. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 20h 21h 22h 23h 24h 25h 26h 27h 1 0 0 1 1 1 vl32 vl33 vl34 vl35 vl36 vl37 vl38 vl39 vgma8 vgma8+(vgma7-vgma8) 100/1660 vgma8+(vgma7-vgma8) 200/1660 vgma8+(vgma7-vgma8) 300/1660 vgma8+(vgma7-vgma8) 400/1660 vgma8+(vgma7-vgma8) 500/1660 vgma8+(vgma7-vgma8) 600/1660 vgma8+(vgma7-vgma8) 700/1660 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 1 0 1 1 1 1 vl40 vl41 vl42 vl43 vl44 vl45 vl46 vl47 vgma8+(vgma7-vgma8) 800/1660 vgma8+(vgma7-vgma8) 900/1660 vgma8+(vgma7-vgma8) 1000/1660 vgma8+(vgma7-vgma8) 1100/1660 vgma8+(vgma7-vgma8) 1210/1660 vgma8+(vgma7-vgma8) 1320/1660 vgma8+(vgma7-vgma8) 1430/1660 vgma8+(vgma7-vgma8) 1540/1660 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 30h 31h 32h 33h 34h 35h 36h 37h 1 1 0 1 1 1 vl48 vl49 vl50 vl51 vl52 vl53 vl54 vl55 vgma7 vgma7+(vgma6-vgma7) 120/4120 vgma7+(vgma6-vgma7) 240/4120 vgma7+(vgma6-vgma7) 370/4120 vgma7+(vgma6-vgma7) 500/4120 vgma7+(vgma6-vgma7) 640/4120 vgma7+(vgma6-vgma7) 780/4120 vgma7+(vgma6-vgma7) 930/4120 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh 1 1 1 1 1 1 vl56 vl57 vl58 vl59 vl60 vl61 vl62 vl63 vgma7+(vgma6-vgma7) 1080/4120 vgma7+(vgma6-vgma7) 1260/4120 vgma7+(vgma6-vgma7) 1470/4120 vgma7+(vgma6-vgma7) 1720/4120 vgma7+(vgma6-vgma7) 2020/4120 vgma7+(vgma6-vgma7) 2520/4120 vgma7+(vgma6-vgma7) 3220/4120 vgma6
6 bit 384 channel rsds source driver S6C1104 13 absolute maximum ratings table 3. absolute maximum ratings (vss1 = vss2 = 0 v) parameter symbol ratings unit logic supply voltage vdd1 -0.3 to 4.0 v driver supply voltage vdd2 -0.3 to 13.0 v vgma1 to 10 -0.3 to vdd2 + 0.3 testi1, testi2 -0.3 to vdd2 + 0.3 input voltage others -0.3 to vdd1 + 0.3 v dio1, dio2 -0.3 to vdd1 + 0.3 output voltage y1 to y384 -0.3 to vdd2 + 0.3 v operating power dissipation pd 300 mw operation temperature top -20 to 75 c storage temperature tstg -55 to 125 c cautions: if lsis are stressed beyond those listed above ?absolute maximum ratings?, they may be permanently destroyed. these are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. turn on power order: vdd1 control signal input vdd2 vgma1 to vgma10 turn off power order: vgma1 to vgma10 vdd2 control signal input vdd1 recommended operation conditions table 4. recommended operation conditions (ta = - 20 to 75 c, vss1 = vss2 = 0 v) parameter symbol min. typ. max. unit logic supply voltage vdd1 2.7 3.0 3.6 v driver supply voltage vdd2 7.0 10.0 12.0 v vgma1 to vgma5 0.5vdd2 - vdd2 - 0.2 v gamma corrected voltage vgma6 to vgma10 vss2+ 0.2 - 0.5vdd2 v driver part output voltage vyo vss2+ 0.2 - vdd2 - 0.2 v maximum clock frequency fmax vdd1 = 2.7v 85 mhz output load capacitance cl - - 150 pf / pin
S6C1104 6 bit 384 channel rsds source driver 14 dc characteristics table 5 . dc characteristics (ta = -20 to 75 c, vdd1 = 2.7 to 3.6 v, vdd2 = 7.0 to 12.0 v, vss1 = vss2 = 0) parameter symbol condition min. typ. max. unit high level input voltage vih 0.7vdd1 - vdd1 low level input voltage vil vss1 - 0.3vdd1 v input leakage current il1 shl, clk1, pol, datpol, dio1 (dio2) - 1 - 1 testi input leak current il2 testi1(testi2) - 1 - 1 a high level output voltage voh dio1(dio2), io = - 1.0 ma vdd1 - 0.5 - - low level output voltage vol dio1(dio2), io = + 1.0 ma - - 0.5 v resistance between gamma voltage r0 to r62 refer to table 1. resistor strings rn 0.7 - rn 1.3 ? ivoh1 vdd2 = 10.0 v, vx (1) = 5.0 v, vyo (2) = 9.0 v - - 0.8 - 0.4 driver output current ivol1 vdd2 = 10.0 v, vx = 5.0 v, vyo = 1.0 v 0.4 0.8 - ma vdd2 = 10.0v vyo = 1.5 v ~ 8.5 v - 3 10 output swing voltage difference deviation dvrms (3) vdd2 = 10.0v vyo = 0.2 v ~ 1.5 v vyo = 8.5 v ~ 9.8 v - - 30 vdd2 = 10.0v vyo = 1.5 v ~ 8.5 v - 20 30 output pin voltage difference deviation dvo vdd2 = 10.0v vyo = 0.2 v ~ 1.5 v vyo = 8.5 v ~ 9.8 v - 30 - mv output average voltage avo vdd2 = 10.0v dxx = 20h (32 g/s) - - 7 mv output voltage range vyo input data: 00h to 3fh vss2 + 0.2 - vdd2 - 0.2 v logic part dynamic current idd1 vdd1 = 3.0 v (4) - - 6 idd2 vdd2 = 10.0v load condition 120pf (5)(6) - - 25 driver part dynamic current idd3 vdd2 = 10.0v no load condition (5)(7) - - 15 ma notes: 1. vx is the voltage applied to analog output pins y1 to y384. 2. vyo is the output voltage of analog output pins y1 to y384. 3. dvrms = max. deviation of (vhx-vlx) vhx; the x gray level positive polarity driver output voltage vlx; the x gray level negative polarity driver output voltage
6 bit 384 channel rsds source driver S6C1104 15 4. clk1 period = 20.68 s raster cycle at fclkp = 65 mhz, input data pattern = 1010 , (checkerboard pattern) alternating data pattern per clkp, ta = 25 c. 5. clk1 period = 20.68 s raster cycle at fclkp = 65 mhz, input data 00h fixed, alternating pol per raster cycle and vgma1 = vdd2-0.2v, vgma10 = vss2 + 0.2v fixed, ta = 25 c. 6. yout load condition : 120pf(tester load). refer to figure 4. 7. yout load condition : no load(yout open). refer to figure 4. vdd1 vdd2 vss2 vss1 y1 y2 y384 dut dut : device under test 0v a a vdd1 vdd2 idd1 idd2 idd3 120pf figure 4. yout load condition(idd2&3)
S6C1104 6 bit 384 channel rsds source driver 16 rsds characteristics table 6 . rsds characteristics (ta = - 20 to 75 c, vdd1 = 2.7 to 3.6 v, vdd2 = 7.0 to 12.0 v, vss1 = vss2 = 0) parameter symbol condition min. typ. max. unit rsds high input voltage vih rsds vcm rsds = + 1.1 v (1) 100 200 - rsds low input voltage vil rsds vcm rsds = + 1.1 v (1) - - 200 - 100 mv rsds common mode input voltage range vcm rsds vih rsds =+100 mv vil rsds =-100 mv (2) 0.9 - 1.3 v rsds input leakage current idl dxxp, dxxn, clkp, clkn - 10 - 10 a notes: 1. vcm rsds =(vclkp+vclkn)/2 or vcm rsds =(vdxxp+vdxxn)/2 2. the positive sign means that dxxp(or clkp) is higher than rsds ground dxxn(or clkn). the negative sign means that dxxp(or clkp) is lower than rsds ground dxxn(or clkn). v rsds n v rsds p vihrsds vilrsds (v rsds p)-(v rsds n) vihrsds 0 v vcmrsds gnd vilrsds figure 5. rsds signal definition
6 bit 384 channel rsds source driver S6C1104 17 ac characteristics table 7. ac characteristics (ta = - 20 to 75 c, vdd1 = 2.7 to 3.6 v, vdd2 = 7.0 to 12.0 v, vss1 = vss2 = 0 v) parameter symbol condition min. typ. max. unit clock pulse width pwclk - 11.7 - - clock pulse low period pwclk(l) - 4 - - clock pulse high period pwclk(h) - 4 - - data setup time tsetup1 (1) 2 - - data hold time thold1 (1) 0 - - start pulse setup time tsetup2 (1) 4 - - start pulse hold time thold2 (1) 2 - - start pulse delay time tplh1 cl = 15pf - - 7.7 ns dio signal pulse width pwdio - 1clkp - 2clkp clk1 setup time tsetup3 - 2clkp - - clk1 high pulse width pwclk1 - 5clkp - - clkp period driver output delay time1 tphl1 (2) (4) - - 6 driver output delay time2 tphl2 (3) (4) - - 10 s last data timing tldt - 1clkp - - clkp period clk1-clkp time tclk1-clkp clk1 clkp 4 - - pol-clk1 time tpol-clk1 pol or clk1 14 - - clk1-pol time tclk1-pol clk1 pol or 10 - - ns notes: (1). vcm rsds = +1.1v , vdiff rsds = v rsds p - v rsds n = 200mv (2). the value is specified when the drive voltage value reaches the target output voltage level of 90% (3). the value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy. (4). yout load condition (refer to figure 6) figure 6. yout load condition y1 y2 y384 30pf 10k ? 20k ? 30pf 20k ? 30pf measure point
S6C1104 6 bit 384 channel rsds source driver 18 waveforms clkp-clkn (rsds) input dio1; shl=h dio2; shl=l dxxp-dxxn (rsds) even odd even odd 1st data 2nd data invalid output dio1; shl=h dio2; shl=l tsetup2 vihrsds 0v vilrsds thold2 70% clkp-clkn vihrsds 0v vilrsds vihrsds 0v vilrsds tsetup1 tsetup1 thold1 thold1 clkp-clkn dxxp-dxxn input dio1; shl=h dio2; shl=l clk1 pol pwdio odd even odd even odd even tplh1 tclk1- clkp 70% 30% 30% 70% tpol-clk1 tldt pwclk1 tclk1-pol 30% 70% 30% 70% invalid pwclk(l) pwclk(h) pwclk 70% 70% 90% y1 to y384 hz tphl1 tphl2 50% 50% 50% 50% 50% 10% 10% 50% 50% 50% 50% 50% 50% figure 7. waveforms
6 bit 384 channel rsds source driver S6C1104 19 relationships between clk1, start pulse (dio1, dio2) and blanking period tldt invalid data clkp-clkn (rsds) dio1 input (dio2 input) clk1 dxxp-dxxn (rsds) min. 2(clkp-clkn) 0.5vdd1 hi-z vgma6 - vgma10 vgma1 - vgma5 clk1 pol y 2n-1 :odd number output y 2n :even number output vgma1 - vgma5 vgma1 - vgma5 vgma6 - vgma10 hi-z hi-z hi-z vgma6 - vgma10 1(clkp-clkn) blanking time = min. 4(clkp-clkn) tsetup3 pwclk 1st data first data in the next line 2nd data nth data n-1th data last data figure 8. waveforms
S6C1104 6 bit 384 channel rsds source driver 20 rsds data timing diagram b[0] 1 b[1] 1 b[0] 2 b[1] 2 b[0] 3 b[1] 3 b[0] 4 b[1] 4 b[2] 1 b[3] 1 b[2] 2 b[3] 2 b[2] 3 b[3] 3 b[2] 4 b[3] 4 b[4] 1 b[5] 1 b[4] 2 b[5] 2 b[4] 3 b[5] 3 b[4] 4 b[5] 4 g[0] 1 g[1] 1 g[0] 2 g[1] 2 g[0] 3 g[1] 3 g[0] 4 g[1] 4 g[2] 1 g[3] 1 g[2] 2 g[3] 2 g[2] 3 g[3] 3 g[2] 4 g[3] 4 g[4] 1 g[5] 1 g[4] 2 g[5] 2 g[4] 3 g[5] 3 g[4] 4 g[5] 4 r[0] 1 r[1] 1 r[0] 2 r[1] 2 r[0] 3 r[1] 3 r[0] 4 r[1] 4 r[2] 1 r[3] 1 r[2] 2 r[3] 2 r[2] 3 r[3] 3 r[2] 4 r[3] 4 r[4] 1 r[5] 1 r[4] 2 r[5] 2 r[4] 3 r[5] 3 r[4] 4 r[5] 4 clkp-clkn input dio: shl=h doi: shl=l d00p/n d01p/n d02p/n d10p/n d11p/n d12p/n d20p/n d21p/n d22p/n tsetup2 thold2 tsetup1 thold1 tsetup1 thold1 figure 9. rsds data timing diagram

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